There is some misinformation in the mail to which Curious Labs has responded. I'll try to claify in normal english. The techies should take a look at http://www6.tomshardware.com/cpu/00q4/001120/p4-10.html which tells you the same, but with a more indepth and complex explanation. First: The P4 does NOT have 6 floating point units. How someone got to this number I can't imagine, but it is just not true! That person probably confused FPUs with execution units, but even then the number 6 is wrong. (just as the 2 for Athlon) Some background: The design goal for the P4 was a chip that had to run at as high clock speed as possible. (no matter what)Furthermore it would feature another extension to SSE to improve performance. The result was that some compromises had to be made which have produced a CPU that acts quite differently (and for some people unpredictable) than its predecessors. One of the compromises is that SSE2 has been introduced, but at the expense of FPU, MMX, and SSE1. And those are less powerfull then on the P3 and Athlon. That isn't a bad thing as long as everybody rewrites their programs and changes the X87FPU instructions into SSE2 instructions. (And as long as they don't mind that their precision goes down from 80bit to 64bit floating point) The result shows very clearly in the benchmarks. In programs which are specially optimized to use SSE2 instructions, the P4 shines, but in code that uses X87 FPU instructions the P4 does poorly compared to P3 and Athlon, because it was designed that way. Poser4 was of course made for X87 FPU instructions. Lots of companies find that changing software to let it make use of SSE2 is difficult, time consuming and thus costly. Therefore you can see that it is only done in very expensive software where reasonably big performance gains can be reached. (Lightwave, 3dsMax etc) The question is whether that is affordable for a small company like Curious Labs, which creates a low priced program: Poser5. Time will tell. (or maybe curious labs) Marc. P.S. For people that don't want to read the entire article I mentioned (or are put off by the technical terms) I've quoted some parts specifically about the FPU performance: "Things look worse if you have a look at the red boxes, which represent the FPU-part of Pentium 4. Please take the time and compare this part to the Pentium III block diagram. You will see that Intel has actually castrated quite a bit of the SSE/MMX part of Pentium 4. Pentium III used to have two MMX and two SSE units, but Pentium 4 has only got one of each. Intel claims that additional units would not have improved the SSE/SSE2, MMX or FPU performance. However, our benchmark results speak a different language." "Intel hopes that software developers will soon replace the old x87-FPU-instructions with the double-precision FP instructions of SSE2, so that Intel's currently false claim that Pentium 4 has the most powerful FPU finally becomes reality. AMD is very impressed with SSE2 as well, which is why it announced to us only a few days ago that the upcoming Hammer-line of x86-64 processors will include SSE2 as well. I personally have my doubts if SSE2 will be able to replace x87-instructions in scientific software. We should not forget that the original FPU is using 80-bit FP-values, not the less exact 64-bit FP-values offered by SSE2."